preliminary t echnical data ADP3418 a rev. prc 7/3/02 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 dual boostrapped 12 v mosfet driver with output disable preliminary technical data features all-in-one synchronous buck driver bootstrapped high-side drive one pwm signal generates both drives anticross-conduction protection circuitry output disable control turns off both mosfets to float output per intel vrm 10 specification applications multiphase desktop cpu supplies single-supply synchronous buck converters general description the ADP3418 is a dual high-voltage mosfet driver optimized for driving two n-channel mosfets which are the two switches in a non-isolated synchronous buck power converter. each of the drivers is capable of driving a 3000 pf load with a 20 ns propagation delay and a 30 ns transition time. one of the drivers can be bootstrapped, and is designed to handle the high-voltage slew rate asso- ciated with floating high-side gate drivers. the ADP3418 includes overlapping drive protection (odp) to prevent shoot-through current in the external mosfets. the od pin shuts off both the high-side and the low-side mosfets to prevent rapid output capacitor discharge during system shutdown. the ADP3418 is specified over the commercial tempera- ture range of 0c to 85c and is available in a thermally- enhanced 8-lead soic package. functional block diagram figure 1. general application circuit. in od vcc overlap protection circuit bst drvh sw drvl pgnd ADP3418 3 in vcc ADP3418 bst d1 drvh sw drvl pgnd to inductor delay od 1v +1v 12v c bst q1 q2 3
?2? rev. prc ADP3418?specifications 1 (vcc = 12 v, bst = 4 v to 26 v, t a = 0c to +85c, unless otherwise noted) preliminary technical data parameter symbol conditions min typ max units supply supply voltage range v cc 4.15 13.2 v supply current i sys bst = 12 v, in = 0 v 5 7 m a od input input voltage high 2.0 v input voltage low 0.8 v input current -1 +1 a propagation delay time 2 tpdl od see figure 2 15 30 ns tpdh od see figure 2 15 30 ns pwm input input voltage high 2.0 v input voltage low 0.8 v input current -1 +1 a high-side driver output resistance, sourcing current v bst ? v sw =12 v 1.75 3.0 ? ? ? ?
?3? rev. prc ADP3418 preliminary technical data pin function descriptions pin name function 1 b s t upper mosfet floating bootstrap supply. a capacitor connected between bst and sw pins holds this bootstrapped voltage for the high-side mosfet as it is switched. the capacitor should be chosen between 100 nf and 1 f. 2 i n logic-level input. this pin has primary control of the drive outputs. 3 od output disable. when low, this pin disables normal operation, forcing drvh and drvl low. 4 vcc input supply. this pin should be bypassed to pgnd with ~1 f ceramic capacitor. 5 drvl synchronous rectifier drive. output drive for the lower (synchronous rectifier) mosfet. 6 p g n d power ground. should be closely connected to the source of the lower mosfet. 7 s w this pin is connected to the buck-switching node, close to the upper mosfet ?s source. it is the float- ing return for the upper mosfet drive signal. it is also used to monitor the switched voltage to prevent turn-on of the lower mosfet until the voltage is below ~1 v. thus, according to operating conditions, the high-low transition delay is determined at this pin. 8 drvh buck drive. output drive for the upper (buck) mosfet. in drvh-sw drvl sw tpdl drvl tf drvl tr drvl tpdl drvh tf drvh tpdh drvh tr drvh v th v th 1v tpdh drvl figure 3. nonoverlap timing diagram (timing is referenced to the 90% and 10% points unless otherwise noted) figure 2. output disable timing diagram drvh or drvl tpdl od tpdh od 90% 10% od
?4? rev. prc outline dimensions dimensions shown in inches and (mm). ADP3418 preliminary technical data 8-lead soic r-8 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8o 0o 0.0196 (0.50) 0.0099 (0.25) 3 45 8 85 4 1 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35)
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